1. Field of the Invention
Embodiments of the present invention relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to a process for depositing and patterning a low k dielectric layer on a substrate.
2. Description of the Related Art
Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.13 μm and even 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
The continued reduction in device geometries has generated a demand for films having lower k values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. In particular, insulators having low dielectric constants (k), less than about 4.0, are desirable.
An effective method to reduce the k value is to introduce pores into dielectric films. As a result, low k films often have a low mechanical strength (e.g., hardness), which may hinder the integration of the films into the manufacture of the device. Plasma post treatment is currently being used to increase the mechanical strength of low k films. However, the plasma treatment causes the k value to increase.
Therefore, there remains a need for a method of forming and patterning low k dielectric layers with good mechanical properties.